View NCP5222_6012847.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2010 february, 2010 ? rev. 0 1 publication order number: NCP5222/d NCP5222 high performance dual-channel / two-phase synchronous buck controller for notebook power system the NCP5222, a fast ? transient ? response and high ? efficiency dual ? channel / two ? phase buck controller with built ? in gate drivers, provides multifunctional power solutions for notebook power system. 180 interleaved operation between the two channels / phases has a capability of reducing cost of the common input capacitors and improving noise immunity. the interleaved operation also can reduce cost of the output capacitors with the two ? phase configuration. input supply voltage feedforward control is employed to deal with wide input voltage range. on ? line programmable and automatic power ? saving control ensures high efficiency over entire load range. fast transient response reduces requirement on the output filters. in the dual ? channel operation mode, the two output power rails are regulated individually. in the two ? phase operation mode, the two output power rails are connected together by an external switch and current ? sharing control is enabled to balance power delivery between phases. features ? wide input voltage range: 4.5 v to 27 v ? adjustable output voltage range: 0.8 v to 3.3 v ? option for dual ? channel and two ? phase modes ? fixed nominal switching frequency: 300 khz ? 180 interleaved operation between the two channels in continue ? conduction ? mode (ccm) ? adaptive power control ? input supply voltage feedforward control ? transient ? response ? enhancement (tre) control ? resistive or inductor?s dcr current sensing ? 0.8% internal 0.8 v reference ? internal 1 ms soft ? start ? output discharge operation ? built ? in adaptive gate drivers ? input supplies undervoltage lockout (uvlo) ? output overvoltage and undervoltage protections ? accurate over current protection ? thermal shutdown protection ? qfn ? 28 package ? this is a pb ? free device typical applications ? cpu chipsets power supplies ? notebook applications device package shipping ? ordering information NCP5222mnr2g qfn28 (pb ? free) 4000 / tape & reel qfn28 case 485ar marking diagram http://onsemi.com a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. vin fb2 comp2 v ccp vcc fb1 p gnd1 drv s / 2ch p gnd2 dl2 dl1 swn2 bst2 cs1 ? / vo1 cs1+ en1/ s kip1 bst1 comp1 ics2 ics1 p good1 p good2 28 27 26 25 24 23 22 8 9 10 11 12 13 14 2 3 5 6 21 20 18 16 15 1 4 7 19 agnd 29 17 NCP5222 cs2 ? / vo2 cs2+ en2/ skip2 dh2 dh1 swn1 (top view) pin connections 1 n5222 alyw
NCP5222 http://onsemi.com 2 figure 1. typical application diagram for a dual ? channel application vo1 en1/skip1 cs1+ cs1+ cs1 ? / vo1 cs1 ? / vo1 vin pgoo d1 pgoo d2 agnd vo2 en2/ski p2 cs2+ cs2+ cs2 ? / vo2 cs2 ? / vo2 vin vi n 5v pgnd vin fb2 co mp2 vccp vcc fb1 pgnd1 drvs / 2ch pgnd2 dl2 dl1 swn2 cs1 ? / vo1 cs1+ en1/ skip1 bst1 co mp1 ics2 ics1 pgo od1 pgo od2 28 27 26 25 24 23 22 8 9 10 11 12 13 14 agnd 29 NCP5222 dh1 swn1 cs2 ? / vo2 cs2+ en2/ skip2 bst2 dn2 1 2 3 4 5 6 7 21 20 19 18 17 16 15
NCP5222 http://onsemi.com 3 figure 2. an application diagram for a two ? phase application vo1 en1/skip1 cs1+ cs1+ cs1 ? / vo1 cs1 ? / vo1 vin pg oo d1 pg oo d2 agnd vo2 en2/ski p2 cs2+ cs2+ cs2 ? / vo2 cs2 ? / vo2 vin vi n 5v pgnd vin fb2 co mp2 vccp vcc fb1 pgnd1 drvs/ 2ch pgnd2 dl2 dl1 swn2 bst2 cs1 ? / vo1 cs1+ en1/ skip1 bst1 co mp1 ics2 ics1 pgoo d1 pgoo d2 28 27 26 25 24 23 22 8 9 10 11 12 13 14 agnd 29 NCP5222 1 2 3 4 5 6 7 19 18 17 16 15 20 21 dh1 swn1 cs2 ? / vo2 cs2+ en2/ skip2 dh2
NCP5222 http://onsemi.com 4 figure 3. functional block diagram pwm control 1 25 gate driver 1 bst1 24 dh1 23 swn1 19 vccp 22 dl1 21 p gnd1 dh_pre1 ov1 3 comp1 2 fb1 1 ics1 28 cs1 ? /vo1 27 cs1+ thermal shut down osc g i skip1 reference generator 4 vin digital soft ? start uv1 oc1 30mv 920mv 1.25v 800mv clk_h clk1 dischg1 dl_pre1 pwm control 2 11 gate driver 2 bst2 12 dh2 13 swn2 vccp 14 dl2 15 p gnd2 dh_pre2 ov2 5 comp2 6 fb2 7 i cs2 8 cs2 ? /vo2 9 cs2+ g i skip2 uv2 oc2 dischg2 dl_pre2 10 en2/skip2 16 pgood2 26 en1/skip1 20 pgood1 clk2 29 agnd por 17 vcc configur ation detection share pgood2 pgood1 2ph g m 18 drvs / 2ch driver for sharing ? fet share 2ph sharing control ss1 ss2 ss1 ss2 cs2 ? cs1 ? 640mv 20k 20k divider & 180 phase shifter
NCP5222 http://onsemi.com 5 pin description pin no. symbol descriptions 1 ics1 current ? sense output 1. output of the current ? sense amplifier of channel 1. 2 fb1 feedback 1. output voltage feedback of channel 1. 3 comp1 comp1. output of the error amplifier of channel 1. 4 vin vin. input supply voltage monitor input. 5 comp2 comp2. output of the error amplifier of channel 2. 6 fb2 feedback 2. output voltage feedback of channel 2. 7 ics2 current ? sense output 2. output of the current ? sense amplifier of channel 2. 8 cs2 ? / vo2 current sense 2 ? . inductor current differential sense inverting input of channel 2. output voltage 2. connection to output of channel 2. 9 cs2+ current sense 2+. inductor current differential sense non ? inverting input of channel 2. 10 en2 / skip2 enable 2. enable logic input of channel 2. skip 2. power ? saving operation (fpwm and skip) programming pin of channel 2. 11 bst2 bootstrap connection 2.channel 2 high ? side gate driver input supply, a bootstrap capacitor connection between swn2 and this pin. 12 dh2 high ? side gate drive 2. gate driver output of the high ? side n ? channel mosfet for channel 2. 13 swn2 switch node 2. switch node between the high ? side mosfet and low ? side mosfet of channel 2. 14 dl2 low ? side gate drive 2. gate driver output of the low ? side n ? channel mosfet for channel 2. 15 pgnd2 power ground 2. ground reference and high ? current return path for the low ? side gate driver of channel 2. 16 pgood2 power good 2. power good indicator of the output voltage of channel 2. (open drained) 17 vcc vcc. this pin powers the control section of ic. 18 drvs / 2ch gate driver for switch. gate driver output for the external switch in dual ? phase configuration. dual ? channel. dual ? channel configuration programming pin. 19 vccp vcc power. this pin powers internal gate drivers. 20 pgood1 power good 1. power good indicator of the output voltage of channel 1. (open drained) 21 pgnd1 power ground 1. ground reference and high ? current return path for the low ? side gate driver of channel 1. 22 dl1 low ? side gate drive 1. gate driver output of the low ? side n ? channel mosfet for channel 1. 23 swn1 switch node 1. switch node between the high ? side mosfet and low ? side mosfet of channel 1. 24 dh1 high ? side gate drive 1. gate driver output of the high ? side n ? channel mosfet for channel 1. 25 bst1 bootstrap connection 1. channel 1 high ? side gate driver input supply, a bootstrap capacitor connection between swn1 and this pin. 26 en1 / skip1 enable 1. enable logic input of channel 1. skip 1. power ? saving operation (fpwm and skip) programming pin of channel 1. 27 cs1+ current sense 1+. inductor current differential sense non ? inverting input of channel 1. 28 cs1 ? / vo1 current sense 1 ? . inductor current differential sense inverting input of channel 1. output voltage 1. connection to output of channel 1. 29 agnd analog ground. low noise ground for control section of ic.
NCP5222 http://onsemi.com 6 maximum ratings rating symbol value unit min max power supply voltages to agnd v cc , v ccp ? 0.3 6.0 v high ? side gate driver supplies: bst1 to swn1, bst2 to swn2 high ? side gate driver voltages: dh1 to swn1, dh2 to swn2 v bst1 ? v swn1 , v bst2 ? v swn2 , v dh1 ? v swn1 , v dh2 ? v swn2 ? 0.3 6.0 v input supply voltage sense input to agnd v in ? 0.3 30 v switch nodes v swn1 , v swn2 ? 0.3, ? 5 (<100 ns) 30 v high ? side gate drive outputs v dh1 , v dh2 ? 0.3, ? 5 (<100 ns) 36 v low ? side gate drive outputs v dl1 , v dl2 ? 0.3, ? 5 (<100 ns) 6.0 v feedback input to agnd v fb1 , v fb2 ? 0.3 6.0 v error amplifier output to agnd v comp1 , v comp2 ? 0.3 6.0 v current sharing output to agnd v ics1 , v ics2 ? 0.3 6.0 v current sense input to agnd v cs1+ , v cs1 ? , v cs2+ , v cs2 ? ? 0.3 6.0 v mode program i/o to pgnd1 v drvs ? 0.3 6.0 v enable input to agnd v en1 , v en2 ? 0.3 6.0 v power good output to agnd v pgood1 , v pgood2 ? 0.3 6.0 v pgnd1, pgnd2 to agnd v gnd ? 0.3 0.3 v operating junction temperature range t j ? 40 150 c operating ambient temperature range t a ? 40 85 c storage temperature range t stg ? 55 150 c thermal characteristics thermal resistance junction to air (pad soldered to pcb) r ja 45 (note 1) c/w moisture sensitivity level msl 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. directly soldered on 4 layer pcb with thermal vias, thermal resistance from junction to ambient with no airflow is around 40~45 c/w (depends on filled vias or not). directly soldered on 4 layer pcb without thermal vias, thermal resistance from junction to ambient with no air flow is around 56 c/w. 2. this device is sensitive to electrostatic discharge. follow proper handing procedures. electrical characteristics (v cc = 5 v, v in = 12 v, t a = ? 40 c to 85 c, unless other noted) characteristics symbol test conditions min typ max unit supply voltage input voltage v in 4.5 ? 27 v v cc operating voltage v cc 4.5 5.0 5.5 v v ccp operating voltage v ccp 4.5 5.0 5.5 v supply current v cc quiescent supply current in fpwm operation ivcc_fpwm en1 = en2 = 1.95 v, fb1 and fb2 forced above regulation point, dh1, dl1, dh2, and dl2 are open 2.5 5 ma 3. guaranteed by design, not tested in production.
NCP5222 http://onsemi.com 7 electrical characteristics (v cc = 5 v, v in = 12 v, t a = ? 40 c to 85 c, unless other noted) characteristics unit max typ min test conditions symbol supply current v cc quiescent supply current in power ? saving operation ivcc_ps en1 = en2 = 5 v, fb1 and fb2 forced above regulation point, dh1, dl1, dh2, and dl2 are open 2.5 5 ma v cc shutdown current ivcc_sd en1 = en2 = 0 v 1 a v ccp quiescent supply current in fpwm operation ivccp_fpwm en1 = en2 = 1.95 v, fb1 and fb2 forced above regulation point, dh1, dl1, dh2, and dl2 are open 0.3 ma v ccp quiescent supply current in power ? saving operation ivccp_ps en1 = en2 = 5 v, fb1 and fb2 forced above regulation point, dh1, dl1, dh2, and dl2 are open 0.3 ma v ccp shutdown current ivccp_sd en1 = en2 = 0 v 1 a bst quiescent supply current in fpwm operation ibst_fpwm en1 = en2 = 1.95 v, fb1 and fb2 forced above regulation point, dh1, dl1, dh2, and dl2 are open 0.3 ma bst quiescent supply current in power ? saving operation ibst_ps en1 = en2 = 5 v, fb1 and fb2 forced above regulation point, dh1, dl1, dh2, and dl2 are open 0.3 ma bst shutdown current ibst_sd en1 = en2 = 0 v, bst1 = bst2 = 5 v, swn1 = swn2 = 0 v 1 a v in supply current (sink) ivin en1 = en2 = 5 v 35 a v in shutdown current ivin_sd en1 = en2 = 0 v 1 a voltage monitor v cc start threshold vccuv+ v cc and v ccp are connected to the same voltage source 4.05 4.25 4.48 v v cc uvlo hysteresis vcchys ? 400 ? 300 ? 200 mv v in start threshold vinuv+ 3.2 3.6 4.0 v v in uvlo hysteresis vinhys ? 700 ? 500 ? 300 mv power good high threshold vpgh pgood goes high from higher vo 105 110 115 % hystersis 5 % power good low threshold vpgl pgood goes high from lower vo 85 90 95 % hystersis ? 5 power good high delay td_pgh 150 s power good low delay td_pgl 1.5 s output overvoltage trip threshold fbovpth fb compared to 0.8 v 110 115 120 % hystersis ? 5 output overvoltage fault latch delay ovptd 1.5 s output undervoltage trip threshold fbuvpth fb compared to 0.8 v 75 80 85 % hystersis 10 output undervoltage protection fault latch blanking time uvptblk ? 27 ? s 3. guaranteed by design, not tested in production.
NCP5222 http://onsemi.com 8 electrical characteristics (v cc = 5 v, v in = 12 v, t a = ? 40 c to 85 c, unless other noted) characteristics unit max typ min test conditions symbol internal reference vfb regulation voltage v fb1 , v fb2 t a = 25 c 0.794 0.8 0.806 v t a = ? 40 c to 85 c 0.792 0.808 switching frequency normal operation frequency f sw t a = 25 c 276 300 324 khz t a = ? 40 c to 85 c 270 330 internal soft ? start soft ? start time t ss 0.8 1 1.2 ms switching regulator ramp offset voltage vramp_offset (note 3) 0.4 v ramp amplitude voltage vramp_v v in = 5 v (note 3) 1.25 v v in = 12 v (note 3) 3 minimum ton ton_min 70 ns minimum toff toff_min 360 ns voltage error amplifier dc gain gain_vea (note 3) 88 db unity gain bandwidth ft_vea (note 3) 15 mhz slew rate sr_vea comp to gnd 100 pf (note 3) 2.5 v/ s output voltage swing vmax_ea isource_ea = 2 ma 3.3 3.6 v vmin_ea isink_ea = 2 ma 0.1 0.3 v differential current sense amplifier cs+ and cs ? common ? mode input signal range vcscom_max refer to agnd 3.5 v v cs to i cs gain ics_gain (ics/vcs) 2ph mode, v cs = v(cs+) ? v(cs ? ) = 4 mv 0.5 a/mv internal resistance from ics to 1.25 v bias rics 20 k ics voltage dynamic range vics_dyn 2ph mode (note 3) 0.75 ~ 1.75 v [v(ics2) ? v(ics1)] to ifb2 gain ifb2_gain (ifb2/(v(ics2) ? v(ics1))) 2ph mode 0.1 a/mv current ? sharing gain ish_gain (ifb2/(vcs2 ? v cs1)) 2ph mode (ifb2/((v(cs2+) ? v(cs2 ? )) ? (v(cs1+) ? v(cs1 ? ))) 1 a/mv ifb2 offset current ifb2_offset 2ph mode, vcs1 = vcs2 = 0 v ? 0.5 0.5 a ifb2 current dynamic range in 2ph mode 2ph mode ? 9 9 a overcurrent protection ocp threshold vth_oc v(cs+) ? v(cs ? ), vo = 0.8 v to 3.3 v 27 30 33 mv ocp fault latch blanking time ocptblk ? 107 ? s sharing switch gate drive soft ? on source current idrvs 1 ma pull ? high resistance rh_drvs 20 pull ? low resistance rl_drvs 10 3. guaranteed by design, not tested in production.
NCP5222 http://onsemi.com 9 electrical characteristics (v cc = 5 v, v in = 12 v, t a = ? 40 c to 85 c, unless other noted) characteristics unit max typ min test conditions symbol configuration detection configuration detection time tcd 53 s pull ? low resistance in detection rl_cd 2 k detection threshold vcd v ccp pin to drvs/2ch pin 0.5 v gate driver dh pull ? high resistance rh_dh1, rh_dh2 2.5 5 dh pull ? low resistance rl_dh1, rl_dh2 1.5 2.5 dl pull ? high resistance rh_dl1, rh_dl2 2 3 dl pull ? low resistance rl_dl1, rl_dl2 0.75 1.5 dead time tlh dl ? off to dh ? on (see figure 4) 10 25 40 ns thl dh ? off to dl ? on (see figure 4) 10 25 40 ns control logic en logic input voltage threshold for disable ven_disable en goes low 0.7 1.0 1.3 v hysteresis 150 200 250 mv en logic input voltage threshold for fpwm ven_fpwm 1.7 1.95 2.25 v en logic input voltage threshold for skip ven_skip en goes high 2.4 2.65 2.9 v hysteresis 100 175 250 mv en source current ien_source en = 0 v (note 3) 0.1 a en sink current ien_sink en = 5 v (note 3) 0.1 a pgood pin on resistance pgood_r i_pgood = 5 ma 70 pgood pin off current pgood_lk 1 a output discharge mode output discharge on ? resistance r discharge en = 0 v, v out = 0.5 v 25 35 thermal shutdown thermal shutdown t sd shutdown threshold (note 3) 150 c hysteresis (note 3) ? 25 c 3. guaranteed by design, not tested in production. t lh 1 v 1 v t hl dh ? swn dl ? pgnd figure 4. dead time between high ? side gate drive and low ? side gate drive
NCP5222 http://onsemi.com 10 general the NCP5222, a fast ? transient ? response and high ? efficiency dual ? channel / two ? phase buck controller with builtin gate drivers, provides multifunctional power solutions for notebook power system. 180 interleaved operation between the two channels / phases has a capability of reducing cost of the common input capacitors and improving noise immunity. the interleaved operation also can reduce cost of the output capacitors with the two ? phase configuration. input supply voltage feedforward control is employed to deal with wide input voltage range. on ? line programmable and automatic power ? saving control ensures high efficiency over entire load range. fast transient response reduces requirement on the output filters. in the dual ? channel operation mode, the two output power rails are regulated individually. in the two ? phase operation mode, the two output power rails are connected together by an external switch and current ? sharing control is enabled to balance power delivery between phases. dual ? channel mode or two ? phase mode the NCP5222 can be externally configured to be working in dual ? channel operation mode or two ? phase operation mode. in the dual ? channel operation mode, the two output power rails are regulated individually. in the two ? phase operation mode, the two output power rails are connected together by an external switch and current ? sharing control is enabled to balance power delivery between phases. figure 5 shows two typical external configurations. in figure 5(a), the controller is configured to operate in the dual ? channel mode by connecting the pin drvs with the pin v ccp . in figure 5(b), the controller is configured to operate in the two ? phase mode. in this mode, an external mosfet ssh is employed to connect the two output power rails together, and the pin drvs of the NCP5222 provides driving signal to ssh. two filter capacitors ccs1 and cics2 are connected with two current ? sense output pins ics1 and ics2, respectively. a typical timing diagram is shown in figure 6. vccp drvs/ 2ch i cs2 i cs1 18 1 7 19 NCP5222 s sh c ics2 vccp drvs/ 2ch ics2 ics1 18 1 7 19 NCP5222 c i cs1 vo2 vo1 s sh ( a ) dual ? c hannel ( b ) two ? phas e figure 5. mode configurations mode detection in the initial stage of the ic powering up, there is mode detection period to read the external setup just after v in and v cc are both ready and at least one of ens is enabled. in figure 6, v in and v cc are powered up first. at 3.5 us after en2 goes high, a 53 s mode detection period starts. the drvs pin is pulled down by an internal 2 k . at the end of the mode detection, if the drvs is higher than v ccp ? 0.5 v the system goes to the dual ? channel mode and leaves drvs high impedance. if the drvs is lower than v ccp ? 0.5 v, the system goes to the two ? phase mode and the drvs pin is pulled down to pgnd1 by an internal 10 fet. drvs softstart in two ? phase mode in the two ? phase mode, the drvs softstart begins after the both pgood1 and pgood2 become valid. during the drvs softstart, 1 ma current is sourced out from the drvs pin and thus voltage in drvs is ramping up. the drvs soft ? start is complete after the drvs voltage is higher than v ccp ? 0.2 v, and then the drvs pin is pulled up to v ccp by an internal 20 fet.
NCP5222 http://onsemi.com 11 en2 en1 vcc vin drvs pgood2 pgood1 vo1 vo2 3.5us 53us 260 us 150us 1ms 67us 57us 1ms 260us 150us 0 .5v 0.2v 3 .6v 4.2 5v en2 goes high and mode detection starts. mode detection complete. system and ch2 reset complete and ch2 soft start begins. ch2 r amping up complet e. ch2 i n regul ati on. pgood2 vali d. en1 goes hi gh and ch1 reset. ch1 sof tst art begins. ch1 rampi ng up complet e. ch1 i n regul ation. pgood1 valid and drvs soft start begins. drvs soft start complet e. ch1 power down. ch2 power down . figure 6. timing diagram in two ? phase mode control logic the NCP5222 monitors v cc with undervoltage lockout (uvlo) function. if v cc is in normal operation range, the converter has a soft ? start after en signal goes high. the internal digital soft ? start time is fixed to 1 ms. the two channels share one dac ramping ? up circuit. if the two ens become high at the same time (within 5 s), the two channels start soft ? start together; if one channel? s en comes when the other channel is powering up, the channel starts powering up after the other channel completes soft start. if one channel?s en comes when the other channel is in any fault condition, the channel does not start powering up until the fault is cleared. the NCP5222 has output discharge operation through one internal 20 mosfet per channel connected from cs ? /vo pin to pgnd pin, when en is low or the channel is under any fault condition. current ? sense network in the NCP5222, the output current of each channel is sensed differentially. a high gain and low offset ? voltage differential amplifier in each channel allows low ? resistance current ? sense resistor or low ? dcr inductor to be used to minimize power dissipation. for lossless inductor current sensing as shown in figure 7, the sensing rc network should satisfy: l dcr r cs1 r cs2 r cs1 r cs2 c cs k cs r cs1 c cs (eq. 1) where the dividing ? down ratio k cs is k cs r cs2 r cs1 r cs2 (eq. 2) dcr is a dc resistance of an inductor, and normally ccs is selected to be around 0.1 f. the current ? sense input voltage across cs+ and cs ? is v cs k cs i l dcr (eq. 3) if there is a need to compensate measurement error caused by temperature, an additional resistance network including
NCP5222 http://onsemi.com 12 a negative ? temperature ? coefficient (ntc) thermistor may be connected with c cs in parallel. cs+ cs ? l dcr rcs1 rcs2 ccs 30mv oc 1 figure 7. current sensing network and overcurrent protection output regulation as shown in figure 8, with a high gain error amplifier and an accurate internal reference voltage, the NCP5222 regulates average dc value of the output voltage to a design target by error integration function. the output has good accuracy over full ? range operation conditions and external component variations. r sq _ q fb ramp clk pwm vref pwm comparator error amplifier figure 8. pwm output regulation output regulation in dual ? channel mode in dual ? channel operation mode, the two channels regulate their output voltage individually. as shown in figure 9, the output voltage is programmed by external feedback resistors. v o 1 r 1 r 4 v ref (eq. 4) where vref is an internal 0.8 v reference voltage. pwm1 l c 0.8v r4 r1 fb vo comp swn figure 9. pwm output regulation in dual ? channel mode output regulation in two ? phase mode figure 10 shows a block diagram for explanation of the output regulation in the two ? phase mode. under the two ? phase configuration, a mosfet ssh called sharing switch is employed to connect two power rails v o1 and v o2 . i share v o2 v o1 r on_s (eq. 5) where r on_s is on resistance of s sh .
NCP5222 http://onsemi.com 13 swn1 swn2 fb2 g i pwm1 rcs11 rcs12 ccs1 l1 c1 cs1+ 0.8v r14 r11 cs1 ? 20k 1.25v g m g i pwm2 rcs21 rcs22 ccs2 l2 c2 cs2+ 0.8v r24 r21 cs2 ? fb1 vo1 vo2 ics1 ics2 comp1 comp2 ifb2 io1 il1 ish io2 il2 ssh rics1 20k rics2 figure 10. pwm output regulation in two ? phase mode in the two ? phase operation, the phase 1 has the same output regulation control as what is in the dual ? channel operation. the output voltage is v o1 1 r 11 r 14 v ref1 1 r 11 r 14 0.8 (eq. 6) however, in order to achieve current ? sharing function, the output voltage in phase 2 is adjusted to be higher or lower than v o1 to balance the power delivery in the two phases, by means of an injection current i fb2 into the phase 2 error amplifier?s non ? inverting node. thus output voltage of the phase 2 is v o2 1 r 21 r 24 v ref2 i fb2 r 21 (eq. 7) 1 r 21 r 24 0.8 i fb2 r 21 the injection current i fb2 is proportional to the dif ference between the two current ? sense output signals v ics2 and v ics1 , that is i fb2 g ifb2 v ics2 v ics1 (eq. 8) 1x10 ? 3 v ics2 v ics1 1x10 ? 4 v ics2 v ics1 1x10 ? 3 k cs2 dcr 2 i l2 k cs1 dcr 1 i l1 where v ics1 g ics1 r ics1 v cs1 v ics_offset (eq. 9) 10 v cs1 1.25 v ics2 g ics2 r ics2 v cs2 v ics_offset (eq. 10) 10 v cs2 1.25 v cs1 k cs1 i l1 dcr 1 (eq. 11) v cs2 k cs2 i l2 dcr 2 (eq. 12) and k cs1 r cs12 r cs11 r cs12 (eq. 13) k cs2 r cs22 r cs21 r cs22 (eq. 14) based on understanding of the power stage connection, the current distribution in the two phases can be calculated by i l1 i o1 i share (eq. 15) and i l2 i o2 i share (eq. 16)
NCP5222 http://onsemi.com 14 where i o1 is the loading current in the power rail v o1 , and i o2 is the loading current in the power rail v o2 . using of equations 5, 6, 7, 8, 15, and 16 gives: i fb2 k il2_ifb2 i o2 k il1_ifb2 i o1 k il1_ifb2 k il2_ifb2 (eq. 17) 1 r 21 r 24 v ref2 1 r 11 r 14 v ref1 r 21 k il1_ifb2 i o1 k il2_ifb2 i o2 r on_s r 21 k il1_ifb2 k il2_ifb2 where k il1_ifb2 g ifb2 g ics1 r ics1 k cs1 dcr 1 (eq. 18) 1x10 ? 3 r cs12 r cs11 r cs12 dcr 1 k il2_ifb2 g ifb2 g ics2 r ics2 k cs2 dcr 2 (eq. 19) 1x10 ? 3 r cs22 r cs21 r cs22 dcr 2 to maintain the output voltage v o2 of the phase 2 in certain regulation window in case of any fault or non ? ideal conditions, such as the sharing switch is broken or has too high on resistance, the injection current i fb2 has magnitude limits as 9 a. as a result, v o2 has a limited adjustable range as 1 r 21 r 24 0.8 8 10 ? 6 r 21 v o2 (eq. 20) 1 r 21 r 24 0.8 9 10 ? 6 r 21 in an ideal case that the sharing switch has very small on resistance and the two phases matches perfectly, the current ? sense input voltages in the two phases are equal, that is i l1 dcr 1 k cs1 i l2 dcr 2 k cs2 (eq. 21) using of equations 15, 16, and 21 gives i l1 dcr 2 k cs2 i o1 i o2 dcr 1 k cs1 dcr 2 k cs2 (eq. 22) i l2 dcr 1 k cs1 i o1 i o2 dcr 1 k cs1 dcr 2 k cs2 (eq. 23) i share dcr 1 k cs1 i o1 dcr 2 k cs2 i o2 dcr 1 k cs1 dcr 2 k cs2 (eq. 24) pwm operation there are two available operation modes, which are forced pwm mode and power ? saving skip mode, selected by two different voltage levels at en pin for each channel, respectively. the operation modes can be external preset or on ? line programmed. the two channels / phases controlled by the NCP5222 share one input power rail. the both channels / phases operate at a fixed 300 khz normal switching frequency in continuous ? conduction mode (ccm). to reduce the common input ripple and capacitors, the two channels / phases operate 180 interleaved in ccm. to speed up transient response and increase system sampling rate, an internal 1.2 mhz high ? frequency oscillator is employed. a digital circuitry divides down the high ? frequency clock clk_h and generates two interleaved 300 khz clocks (clk1 and clk2), which are delivered to the two pwm control blocks as normal operation clocks. forced ? pwm operation (fpwm mode) if the voltage level at the en pin is a medium level around 1.95 v, the corresponding channel of the NCP5222 works under forced ? pwm mode with fixed 300 khz switching frequency. in this mode, the low ? side gate ? drive signal is forced to be the complement of the high ? side gate ? drive signal and thus the converter always operates in ccm. this mode allows reverse inductor current, in such a way that it provides more accurate voltage regulation and fast transient response. during soft ? start operation, the NCP5222 automatically runs in fpwm mode regardless of the en pin?s setting to guarantee smooth powering up. pulse ? skipping operation (skip mode) skip mode is enabled by pulling en pin higher than 2.65 v, and then the corresponding channel works in pulse ? skipping enabled operation. in medium and high load range, the converter still runs in ccm, and the switching frequency is fixed to 300 khz. if the both channels run in ccm, they operate interleaved. in light load range, the converter automatically enters diode emulation and skip mode to maintain high efficiency. the pwm on ? time in discontinuous ? conduction mode (dcm) is adaptively controlled to be similar to the pwm on ? time in ccm. transient response enhancement (tre) for a conventional trailing ? edge pwm controller in ccm, the minimum response delay time is one switching period in the worst case. to further improve transient response, a transient response enhancement circuitry is introduced to the NCP5222. the controller continuously monitors the comp signal, which is the output voltage of the error amplifier, to detect load transient events. a desired stable close ? loop system with the NCP5222 has a ripple voltage in the comp signal, which peak ? to ? peak value is normally in a range from 200 mv to 500 mv. there is a threshold voltage in each channel made in a way that a filtered comp signal pluses an offset voltage. once a large
NCP5222 http://onsemi.com 15 load transient occurs, the comp signal is possible to exceed the threshold and then tre is tripped in a short period, which is typically around one normal switching cycle. in this short period, the controller runs at higher frequency and therefore has faster response. after that the controller comes back to normal operation. protection funtions the NCP5222 provides comprehensive protection functions for the power system, which include input power supply undervoltage lock out, output overcurrent protection, output overvoltage protection, output undervoltage protection, and thermal shutdown protection. the priority of the protections from high to low as: 1. thermal protection and input power supply undervoltage lockout; 2. output overvoltage protection; 3. output overcurrent protection and output undervoltage protection. input power supply undervoltage lock out (uvlo) the NCP5222 provides uvlo functions for both input power supplies (v in and v cc ) of the power stage and controller itself. the two uvlo functions make it possible to have flexible power sequence between v in and v cc for the power systems. the start threshold of v in is 3.6 v, and the starting threshold of v cc is 4.25 v. output overcurrent protection (ocp) the NCP5222 protects converter if overcurrent occurs. the current through each channel is continuously monitored with differential current sense. if inductor current exceeds the current threshold, the high ? side gate drive will be turned off cycle ? by ? cycle. in the meanwhile, an internal oc fault timer will be triggered. if the fault still exists after about 53 s, the corresponding channel latches off, both the high ? side mosfet and the low ? side mosfet are turned off. the fault remains set until the system has shutdown and re ? applied v cc and/or the enable signal en has toggled states. current limit threshold v th_oc between cs+ and cs ? is internally fixed to 30 mv. the current limit can be programmed by the inductor?s dcr and the current ? sense resistor divider with r cs1 and r cs2 . the inductor peak current limit is i oc(peak) v th_oc k cs dcr (eq. 25) the dc current limit is i oc i oc(peak) v o v in v o 2 v in f sw l (eq. 26) where v in is input supply voltage of the power stage, and f sw is 300 khz normal switching frequency. in the dual ? channel mode, the steady ? state inductor dc current is equal to output loading current i omax per channel, so that the overcurrent threshold i oc is the maximum loading current i omax per channel. i oc1 i o1max (eq. 27) i oc2 i o2max (eq. 28) in two ? phase operation mode, to make sure the ocp is not triggered in the normal operation, the worst case need to be considered, in which the maximum load step in one power rail comes just after the two phases are sharing the maximum load from the other power rail. in this case, the two overcurrent thresholds need to be set as i oc1 i o1max dcr 2 k cs2 dcr 1 k cs1 dcr 2 k cs2 (eq. 29) and i oc2 i o2max dcr 1 k cs1 dcr 1 k cs1 dcr 2 k cs2 (eq. 30) the both phases also has the same internal overcurrent current ? sense threshold v th_oc = 30 mv, that means i oc1 dcr 1 k cs1 i oc2 dcr 2 k cs2 v th_oc (eq. 31) use of equations 29, 30, and 31 leads to: i oc1 i o1max 1 i o2max i o1max i o2max (eq. 32) i oc2 i o2max 1 i o1max i o1max i o2max (eq. 33) output overvoltage protection (ovp) an ovp circuit monitors the feedback voltages to prevent loads from over voltage. ovp limit is typically 115% of the nominal output voltage level, and the hysteresis of the ov detection comparator is 5% of the nominal output voltage. if the ov event lasts less than 1.5 s, the controller remains normal operation when the output of the ov comparator is released, otherwise an ov fault is latched after 1.5 s. after the fault is latched, the high ? side mosfet is latched off and the low ? side mosfet will be on and off responding to the output of the ov detection comparator. the fault remains set until the system has shutdown and re ? applied v cc and/or the enable signal en has toggled states. output undervoltage protection (uvp) a uvp circuit monitors the feedback voltages to detect undervoltage. uvp limit is typically 80% of the nominal output voltage level. if the output voltage is below this threshold, a uv fault is set. if an ov protection is set before, the uv fault will be masked. if no ov protection set, an internal fault timer will be triggered. if the fault still exists after about 27 s, the corresponding channel is latches off, both the high ? side mosfet and the low ? side mosfet are
NCP5222 http://onsemi.com 16 turned off. the fault remains set until the system has shutdown and re ? applied v cc and/or the enable signal en has toggled states. thermal protection the NCP5222 has a thermal shutdown protection to protect the device itself from overheating when the die temperature exceeds 150 c. after the thermal protection is triggered, the fault state can be ended by re ? applying v cc or en when the die temperature drops down below 125 c. layout guidelines figures 11 and 12 show exemplary layout of the power stage components for dual ? channel configuration and two ? phase configuration, respectively. in the two ? phase mode, after the sharing switch is turned on, the voltage difference across the sharing ? switch will cause a current flow through it, which is used to balance power delivery between the two phases. the smaller r ds(on) of the sharing switch (r on_ssh ), the better the current balance and the smaller output voltage deviation in v o2 . actually, the current through the sharing switch can be calculated by i ssh = (v o2 ? v o1 ) / r on_effective , in which r on_effective = r on_ssh + r pcb , and r pcb is the copper resistance between the two output sensing points. so that too large r pcb effectively wastes r ds(on) of the sharing switch, and thus reduces the power sharing capability and enlarges v o2 deviation. in a real application, to make sure the ch1 has perfect voltage regulation, the v o1 sensing point and agnd can be designed like remote sensing. in the meantime, to fully use the sharing switch for the current sharing operation and reduce v o2 deviation, the distance between the two sensing points v o1 and v o2 should be arranged to be as close as possible. figure 11. layout guidelines in dual ? channel mode
NCP5222 http://onsemi.com 17 figure 12. layout guidelines in two ? phase mode
NCP5222 http://onsemi.com 18 typical operating characteristics 0.792 0.794 0.796 0.798 0.8 0.802 0.804 0.806 0.808 ? 40 ? 20 0 20 40 60 80 100 120 figure 13. reference voltage v fb vs. ambient temperature t a , ambient temperature ( c) v fb , fb voltage (v) figure 14. switching frequency vs. ambient temperature 270 280 290 300 310 320 330 ? 40 ? 20 0 20 40 60 80 100 120 t a , ambient temperature ( c) f sw , switching frequency (khz) 27 28 29 30 31 32 33 ? 40 ? 20 0 20 40 60 80 100 120 t a , ambient temperature ( c) v th_oc , ocp threshold (mv) figure 15. ocp threshold vs. ambient temperature 2 2.2 2.4 2.6 2.8 3 ? 40 ? 20 0 20 40 60 80 100 12 0 figure 16. v cc quiescent current vs. ambient temperature in fpwm mode t a , ambient temperature ( c) i vcc_fpwm , v cc quiescent current (ma) 2 2.2 2.4 2.6 2.8 3 ? 40 ? 20 0 20 40 60 80 100 120 t a , ambient temperature ( c) i vcc_ps , v cc quiescent current (ma) figure 17. v cc quiescent current vs. ambient temperature in skip mode 0 0.2 0.4 0.6 0.8 1 ? 40 ? 20 0 20 40 60 80 100 120 t a , ambient temperature ( c) figure 18. v cc shutdown current vs. ambient temperature i vcc_sd , v cc shutdown current ( a)
NCP5222 http://onsemi.com 19 typical operating characteristics 4 4.1 4.2 4.3 4.4 4.5 ? 40 ? 20 0 20 40 60 80 100 120 figure 19. v cc start threshold vccuv+ vs. ambient temperature t a , ambient temperature ( c) v ccuv+ , v cc start threshold (v) ? 400 ? 360 ? 320 ? 280 ? 240 ? 200 ? 40 ? 20 0 20 40 60 80 100 120 t a , ambient temperature ( c) figure 20. v cc uvlo hysteresis vcchys vs. ambient temperature 3 3.2 3.4 3.6 3.8 4 ? 40 ? 20 0 20 40 60 80 100 120 figure 21. v in start threshold vinuv+ vs. ambient temperature i o , output current (a) f sw , switching frequency (khz) v cchys , v cc uvlo hysteresis (mv) ? 700 ? 620 ? 540 ? 460 ? 380 ? 300 ? 40 ? 20 0 20 40 60 80 100 12 0 t a , ambient temperature ( c) v inhys , v in uvlo hysteresis (mv) figure 22. v in uvlo hysteresis vinhys vs. ambient temperature 0 50 100 150 200 250 300 350 0 4 8 12 16 20 t a , ambient temperature ( c) v inuv+ , v in start threshold (v) figure 23. switching frequency vs. output current in skip mode v in = 5 v v in = 12 v v in = 20 v 296 297 298 299 300 301 302 048121620 i o , output current (a) f sw , switching frequency (khz) figure 24. switching frequency vs. output current in fpwm mode v in = 5 v v in = 12 v v in = 20 v
NCP5222 http://onsemi.com 20 typical operating characteristics 1.049 1.05 1.051 1.052 1.053 1.054 1.055 0.1 1 10 100 i o , output current (a) v out , output voltage (v) v in = 5 v v in = 12 v v in = 20 v figure 25. output voltage vs. output current in skip mode 1.049 1.05 1.051 1.052 1.053 1.054 1.055 0 4 8 121620 i o , output current (a) v out , output voltage (v) v in = 20 v v in = 12 v v in = 5 v figure 26. output voltage vs. output current in fpwm mode 20 30 40 50 60 70 80 90 100 0.1 1 10 100 i o , output current (a) efficiency (%) v in = 5 v v in = 12 v v in = 20 v figure 27. efficiency vs. output current in skip mode 20 30 40 50 60 70 80 90 100 0.1 1 10 1 0 i o , output current (a) efficiency (%) figure 28. efficiency vs. output current in fpwm mode v in = 20 v v in = 12 v v in = 5 v
NCP5222 http://onsemi.com 21 typical operating characteristics figure 29. input voltage ripple (v in = 12 v, c in = 10 f * 4, v o1 = 1.05 v, i o1 = 10 a, l1 = 0.56 h, c o1 = 470 f * 2, v o2 = 1.05 v, i o2 = 10 a, l2 = 0.56 h, c o2 = 470 f * 2, dual ? channel operation) figure 30. output voltage ripple (v in = 12 v, v o1 = 1.05 v, i o1 = 10 a, l1 = 0.56 h, c o1 = 470 f * 2, v o2 = 1.05 v, i o2 = 10 a, l2 = 0.56 h, c o2 = 470 f * 2, dual ? channel operation) figure 31. powerup with two ens together (v in = 12 v, v o1 = 1.05 v, i o1 = 0 a, v o2 = 1.05 v, i o2 = 0 a, dual ? channel operation) figure 32. powerup with en2 comes before ch1 completes soft ? start (v in = 12 v, v o1 = 1.05 v, i o1 = 0 a, v o1 = 1.05 v, i o2 = 0 a, dual ? channel operation) figure 33. powerup with en2 comes after ch1 completes soft ? start (v in = 12 v, v o1 = 1.05 v, i o1 = 0 a, v o2 = 1.05 v, i o2 = 0 a, dual ? channel operation) figure 34. powerdown and soft ? stop (v in = 12 v, v o1 = 1.05 v, i o1 = 0 a, v o2 = 1.05 v, i o2 = 0 a, dual ? channel operation)
NCP5222 http://onsemi.com 22 typical operating characteristics figure 35. powerup operation without biased output (v in = 12 v, v o = 1.05 v, i o = 0 a, skip mode) figure 36. powerup operation with biased output (v in = 12 v, v o = 1.05 v, i o = 0 a, skip mode) figure 37. power ? down operation (v in = 12 v, v o = 1.05 v, i o = 0 a, skip mode) figure 38. on ? line mode transition (v in = 12 v, v o = 1.05 v, i o = 0.5 a, fpwm ? skip ? fpwm mode) figure 39. load transient response in skip mode (v in = 12 v, v o = 1.05 v, i o = 0.1 a to 10 a to 0.1 a, l = 0.56 h, c o = 470 f * 2) figure 40. load transient response in fpwm mode (v in = 12 v, v o = 1.05 v, i o = 0.1 a to 10 a to 0.1 a, l = 0.56 h, c o = 470 f * 2)
NCP5222 http://onsemi.com 23 typical operating characteristics figure 41. line transient response (v in = 12 v to 20 v, v o1 = 1.05 v, i o1 = 9 a, l1 = 0.56 h, c o1 = 470 f * 2, v o2 = 1.05 v, i o2 = 9 a, l2 = 0.56 h, c o2 = 470 f * 2, dual ? channel mode) figure 42. line transient response (v in = 20 v to 12 v, v o1 = 1.05 v, i o1 = 9 a, l1 = 0.56 h, c o1 = 470 f * 2, v o2 = 1.05 v, i o2 = 9 a, l2 = 0.56 h, c o2 = 470 f * 2, dual ? channel mode) figure 43. powerup with en1 in two ? phase mode (v in = 12 v, v o1 = 1.05 v, i o1 = 0 a, v o2 = 1.05 v, i o2 = 0 a) figure 44. powerdown with en1 in two ? phase mode (v in = 12 v, v o1 = 1.05 v, i o1 = 0 a, v o2 = 1.05 v, i o2 = 0 a) figure 45. powerup with two ens together in two ? phase mode (v in = 12 v, v o1 = 1.05 v, i o1 = 0 a, v o2 = 1.05 v, i o2 = 0 a) figure 46. powerdown with two ens together in two ? phase mode (v in = 12 v, v o1 = 1.05 v, i o1 = 0 a, v o2 = 1.05 v, i o2 = 0 a)
NCP5222 http://onsemi.com 24 figure 47. schematic of evaluation board
NCP5222 http://onsemi.com 25 figure 48. layout of evaluation board
NCP5222 http://onsemi.com 26 bill of materials for evaluation board item part reference description package part number manufacturer qty 1 u1 dual ? channel / two ? phase synchronous buck controller qfn28 (4x4 mm) NCP5222mnr2g on semiconductor 1 2 m11 m21 q1 q2 small signal mosfet 60 v, 115 ma, n ? channel sot ? 23 2n7002lt1g on semiconductor 4 3 q3 small signal mosfet 30 v, 270 ma, n ? channel sc ? 70 nts4001nt1g on semiconductor 1 4 m12 m14 m22 m24 power mosfet 30 v, 58.5 a, single n ? channel so ? 8 flat lead ntmfs4821nt1g on semiconductor 4 5 m13 m15 m23 m25 power mosfet 30 v, 85 a, single n ? channel so ? 8 flat lead ntmfs4847nt1g on semiconductor 4 6 m1 power mosfet 30 v, 191 a, single n ? channel so ? 8 flat lead ntmfs4833nt1g on semiconductor 0 7 d1 schottky diode, dual, common anode, 30 v sot ? 23 bat54alt1g on semiconductor 1 8 d12 d22 led, smt, 2 mm, grn 0805 l ? 0170gct para light 2 9 c11 c21 mlcc cap 50 v, 22 pf, 5%, char: cog 0603 c1608c0g1h220j tdk 2 10 c12 c22 mlcc cap 50 v, 330 pf, 5%, char: cog 0603 c1608c0g1h331j tdk 2 11 c13 c23 mlcc cap 50 v, 820 pf, 5%, char: cog 0603 c1608c0g1h821j tdk 2 12 c1 c4 mlcc cap 50 v, 2.2 nf, 5%, char: cog 0603 c1608c0g1h222j tdk 0 13 c5 mlcc cap 50 v, 10 nf, 5%, char: cog 0603 c1608c0g1h103j tdk 1 14 c2 mlcc cap 50 v, 15 nf, 10%, char: x7r 0603 c1608x7r1h153k tdk 1 15 cb1 cb2 cs1 cs2 mlcc cap 50 v, 0.1 f, 10%, char: x7r 0603 c1608x7r1h104k tdk 4 16 c3 mlcc cap 16 v, 1 f, 10%, char: x5r 0805 c2012x7r1c105k tdk 1 17 c41 mlcc cap 6.3 v, 3.3 f, 10%, char: x5r 0603 c1608jb0j335kt tdk 1 18 c6 c16 c26 0603 0 19 c111 c222 mlcc cap 6.3 v, 10 f, 10%, char: x5r 0805 ecj2fb0j106m panasonic 2 20 cin1 cin2 cin3 cin4 mlcc cap 25v, 10 f, 20%, char: x5r 1812 c4532x7r1e106m tdk 4 21 c17 c18 c27 c28 sp ? capacitors, 2 v, 470 f, esr = 4.5 m 7.3mm x 4.3mm eefsx0d471xr panasonic 4 22 rb1 rb2 thick film chip resistors, 3.3 , 1%, 0.1 w 0603 erj3bsf3r3v panasonic 2 23 r1 r5 thick film chip resistors, 20 , 1%, 0.1 w 0603 erj3ekf20r0v panasonic 2 24 r13 r23 thick film chip resistors, 100 , 1%, 0.1 w 0603 erj3ekf1000v panasonic 2 25 r18 r19 thick film chip resistors, 1 k , 1%, 0.1 w 0603 erj3ekf1001v panasonic 2 26 r16 r26 thick film chip resistors, 3.9 k , 1%, 0.1 w 0603 erj3ekf3901v panasonic 2
NCP5222 http://onsemi.com 27 bill of materials for evaluation board item qty manufacturer part number package description part reference 27 r11 r21 thick film chip resistors, 5.1 k , 1%, 0.1 w 0603 erj3ekf5101v panasonic 2 28 r15 r25 thick film chip resistors, 16 k , 1%, 0.1 w 0603 erj3ekf1602v panasonic 2 29 r14 r24 thick film chip resistors, 16.2 k , 1%, 0.1 w 0603 pcf0603r 16k2bi welwtn 2 30 r9 r10 thick film chip resistors, 39 k , 1%, 0.1 w 0603 erj3ekf3902v panasonic 2 31 r6 r7 r8 r20 thick film chip resistors, 62 k , 1%, 0.1 w 0603 erj3ekf6202v panasonic 4 32 r12 r22 thick film chip resistors, 91 k , 1%, 0.1 w 0603 erj3ekf9102v panasonic 2 33 r29 r30 thick film chip resistors, 86.6 k , 1%, 0.1 w 0603 pcf0603r 86k6bi welwtn 2 34 r2 r3 r28 thick film chip resistors, 100 k , 1%, 0.1 w 0603 erj3ekf1003v panasonic 3 35 r4 r17 r27 0603 0 36 l1 l2 power choke 0.56 h, dcrtyp=1.4 m , isat = 22.9 a 11.2mm x 10.0mm fdu1040d ? r56m toko 2 37 tt1, tt2, tt3, tt4, tt00, tt01, tt21, tt22 pcb terminal 7.54mm, f = 3.18 mm h ? 2121 harwin 8 38 tp11 tp12 tp13 tp14, tp21 tp22 tp23 tp24, jp1 jp2 jp4 jp5, t3 t4 t5 t6 j3 tht header pitch = 2.54 mm; height = 12 mm 547 ? 3302 rs components 17 39 j1 j2 smb ? connectors, impedance = 50 w 295 ? 5665 rs components 2 40 sw1 sw2 sw3 sw4 nkk 4
NCP5222 http://onsemi.com 28 package dimensions qfn28 4x4, 0.4p case 485ar ? 01 issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ???? ???? ???? ???? a d e b c 0.10 pin one reference top view side view bottom view a k d2 e2 c c 0.10 c 0.10 c 0.08 a1 seating plane e 28x note 3 b 28x 0.07 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 b 0.15 0.25 d 4.00 bsc d2 2.50 2.70 e 4.00 bsc e2 2.50 2.70 e 0.40 bsc k l 0.30 0.50 8 15 22 28x 0.40 pitch 4.30 0.62 4.30 dimensions: millimeters 0.26 28x 1 l a3 0.20 ref mounting footprint* note 4 a3 pin 1 indicator 2.71 2.71 1 package outline l1 detail a l alternate terminal constructions l 0.10 c a b b 0.10 c a b b l1 ??? 0.15 0.30 ref recommended *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP5222/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of NCP5222

	To Download NCP5222 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .